1. Field of the Invention
This invention relates to methods of manufacturing a package substrate, and particularly, to a method of manufacturing a package substrate for use in a miniaturized product.
2. Description of Related Art
With the blooming of the electronic industry, an electronic product generally develops with a compact size, multiple functions and high performance. To meet the miniaturization requirement, a package substrate that is used to carry a chip preferably has a reduced thickness. Currently, the package substrate is made of a hard material or a soft material. For instance, a package substrate used in a ball grid array (BGA) package is made of a hard material.
Referring to FIGS. 1A to 1C, cross-sectional views illustrating a method of manufacturing a package substrate 1 having two circuit layers according to the prior art are provided.
As shown in FIG. 1A, two core layers 10 are provided, each of the core layers 10 has a first surface 10a and a second surface 10b opposing the first surface 10a, a first metal layer 11a and a second metal layer 11b are formed on the first surface 10a and the second surface 10b, respectively, and a plurality of through holes 100 connect the first and second surface 10a and 10b. 
As shown in FIG. 1B, a patterning process is performed. Through the first and second metal layers 11a and 11b (using a conductive layer 12 to electroplate metal), first and second circuit layers 13a and 13b are formed on the first and second surfaces 10a and 10b, respectively. Additionally, a conductive via 14 is formed in each of the through hole 100 to electrically connect the first and second circuit layers 13a and 13b. The first and second circuit layers 13a and 13b have a plurality of first and second conductive pads 130a and 130b, respectively.
As shown in FIG. 1C, first and second insulating protection layers 15a and 15b are formed on the first and second surfaces 10a and 10b of the core layer 10, respectively. The first and second insulating protection layers 15a and 15b have a plurality of first and second openings 150a and 150b, respectively, allowing the first and second conductive pads 130a and 130b to be exposed from the first and second opening 150a and 150b, respectively. Sequentially, first and second surface treatment layers 16a and 16b are formed on the exposed surfaces of the first and second conductive pads 130a and 130b, respectively.
In subsequent processes, a chip is mounted on the second insulating protection layer 15b, and a molding process is then performed to obtain a package structure. In order to meet the miniaturization and reliability requirements, the core layer 10 has a thickness S reduced to as small as 60 μm.
However, the core layer 10 having the thickness of 60 μm no longer meets the modern miniaturization requirement. If the thickness S of the core layer 10 is less than 60 μm, the package substrate 1 has a thickness S less than 150 μm. Such a thin package substrate is easily to be damaged during transportation or packaging.
Therefore, how to solve the problem that the miniaturization is contradictory to the reliability is becoming one of the most popular issues in the art.